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INTEGRATED CIRCUITS
PCA9546 4-channel I2C switch with reset
Product data sheet Supersedes data of 2002 Feb 19 2004 Sep 30
Philips Semiconductors
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DESCRIPTION
The PCA9546 is a quad bi-directional translating switch controlled by the I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable Control Register. An active-LOW reset input allows the PCA9546 to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C state machine and causes all the channels to be deselected as does the internal power on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9546. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
FEATURES
* 1-of-4 bi-directional translating switches * I2C interface logic; compatible with SMBus standards * Active LOW Reset Input * 3 address pins allowing up to 8 devices on the I2C-bus * Channel selection via I2C-bus, in any combination * Power-up with all switch channels deselected * Low RdsON switches * Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and * No glitch on power-up * Supports hot insertion * Low stand-by current * Operating power supply voltage range of 2.3 V to 5.5 V * 5 V tolerant Inputs * 0 kHz to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latchup testing is done to JESDEC Standard JESD78 which * Packages offered: SO16, TSSOP16
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic TSSOP TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C exceeds 100 mA 150 V MM per JESD22-A115 and 1000 V per JESD22-C101 5 V buses
ORDER CODE PCA9546D PCA9546PW
DRAWING NUMBER SOT109-1 SOT403-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
PIN CONFIGURATION -- SO, TSSOP
A0 1 A1 2 16 VDD 15 SDA 14 SCL 13 A2 12 SC3 11 SD3 10 SC2 9 SD2
PIN DESCRIPTION
SO, TSSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL A0 A1 RESET SD0 SC0 SD1 SC1 VSS SD2 SC2 SD3 SC3 A2 SCL SDA VDD FUNCTION Address input 0 Address input 1 Active LOW reset input Serial data 0 Serial clock 0 Serial data 1 Serial clock 1 Supply ground Serial data 2 Serial clock 2 Serial data 3 Serial clock 3 Address input 2 Serial clock line Serial data line Supply voltage
RESET 3 SD0 4 SC0 5 SD1 6 SC1 7 VSS 8
SW00913
Figure 1. Pin configuration -- SO, TSSOP
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
BLOCK DIAGRAM
PCA9546
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC VSS
VDD RESET
RESET CIRCUIT
SCL INPUT FILTER I2C-BUS CONTROL
A0 A1 A2
SDA
SW00914
Figure 2. Block diagram
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9546 is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9546 has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 1. Control Register; Write -- Channel Selection/ Read -- Channel Status D7 D6 D5 D4 B3 B2 B1 B0 0 X X X X X X X 1 COMMAND Channel 0 disabled Channel 0 enabled Channel 1 disabled Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled No channel selected; power-up/reset default state
1
1
1
0
A2
A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW00915
Figure 3. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9546, which will be stored in the control register. If multiple bytes are received by the PCA9546, it will save the last byte received. This register can be written and read via the I2C-bus.
CHANNEL SELECTION BITS (READ/WRITE) 7 X 6 X 5 X 4 X 3 B3 2 B2 1 B1 0 B0 CHANNEL CHANNEL CHANNEL CHANNEL 0 1 2 3
0 X X X X X X 1 0 X X X X X 1 0 X X X X 1 X X X X X X
0
0
0
0
0
0
0
0
SW01026
Figure 4. Control register
NOTE: Several channels can be enabled at the same time. Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are disabled and channel 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
RESET INPUT
The RESET input is an active-LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tWL, the PCA9546 will reset its registers and I2C state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor.
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds the PCA9546 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9546 registers and I2C state machine are initialized to their default states, all zeroes causing all the channels to be deselected.
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9546 are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another.
Vpass vs. VDD 5.0 4.5 MAXIMUM 4.0 TYPICAL 3.5 Vpass 3.0 2.5 2.0 1.5 1.0 2.0 2.5 3.0 3.5 4.0 VDD 4.5 5.0 5.5 MINIMUM
Figure 5 shows the voltage characteristics of the pass gate transistors (note that the PCA9546 is only tested at the points specified in the DC Characteristics section of this datasheet). In order for the PCA9546 to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 5, we see that Vpass (max.) will be at 2.7 V when the PCA9546 supply voltage is 3.5 V or lower so the PCA9546 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 12). More Information can be found in Application Note AN262 PCA954X family of I 2C/SMBus multiplexers and switches.
SW00820
Figure 5. Vpass voltage vs. VDD
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 7).
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 6).
System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 8).
SDA
SCL data line stable; data valid change of data allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 7. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement
SW00368
Figure 9. Acknowledgement on the
I2C-bus
SLAVE ADDRESS
CONTROL REGISTER
SDA
S
1
1
1
0
A2
A1
A0
0 R/W
A
X
X
X
X
B3
B2
B1
B0
A
P
start condition
acknowledge from slave
acknowledge from slave
SW00917
Figure 10. WRITE control register
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
S
1
1
1
0
A2
A1
A0
1 R/W
A
X
X
X
X
B3
B2
B1
B0
NA
P stop condition
start condition
acknowledge from slave
no acknowledge from master
SW00918
Figure 11. READ control register
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
TYPICAL APPLICATION
VDD = 2.7 - 5.5 V VDD = 3.3 V V = 2.7 - 5.5 V
SDA SCL
SDA SCL
SD0 CHANNEL 0 SC0 V = 2.7 - 5.5 V
RESET
I2C/SMBus MASTER
SD1 CHANNEL 1 SC1 V = 2.7 - 5.5 V
SD2 CHANNEL 2 SC2 V = 2.7 - 5.5 V A2 A1 A0 VSS SD3 CHANNEL 3 SC3
PCA9546
SW00919
Figure 12. Typical application
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI II IO IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current DC output current Supply current Supply current total power dissipation Storage temperature range Operating ambient temperature CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 20 25 100 100 400 -60 to +150 -40 to +85 UNIT V V mA mA mA mA mW C C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Istb VPOR VIL VIH IO OL IL Ci VIL VIH ILI Ci Pass Gate RO ON Supply voltage Supply current Standby current
VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. (See page 11 for VDD = 3.6 V to 5.5 V) PARAMETER TEST CONDITIONS LIMITS MIN 2.3 Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS no load; VI = VDD or VSS -- -- -- -0.5 0.7VDD VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS 3 6 -1 -- -0.5 0.7VDD pin at VDD or VSS VI = VSS VCC = 3.67 V; VO = 0.4 V; IO = 15 mA VCC = 2.3 V to 2.7 V; VO = 0.4V; IO = 10 mA Vswin = VDD = 3.3 V; Iswout = -100 A VPass Switch output voltage Vswin = VDD = 3.0 V to 3.6 V; Iswout = -100 A Vswin = VDD = 2.5 V; Iswout = -100 A Vswin = VDD = 2.3 V to 2.7 V; Iswout = -100 A IL Cio Leakage current Input/output capacitance VI = VDD or VSS VI = VSS -1 -- 5 7 -- 1.6 -- 1.1 -1 -- TYP -- 40 20 1.6 -- -- -- -- -- 12 -- -- -- 1.6 20 26 2.2 -- 1.5 -- -- 3 MAX 3.6 100 100 2.1 0.3VDD 6 -- -- +1 13 +0.3VDD VDD + 0.5 +1 3 30 55 -- 2.8 -- 2.0 +1 5 A pF V UNIT
V A A V V V mA A pF V V A pF
Power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW level output current LOW-level Leakage current Input capacitance LOW-level input voltage HIGH-level input voltage Input leakage current Input capacitance
Input SCL; input/output SDA
Select inputs A0 to A2 / RESET
Switch resistance
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Istb VPOR VIL VIH IO OL IIL IIH Ci VIL VIH ILI Ci Pass Gate RON VPass IL Cio Supply voltage Supply current Standby current
VDD = 3.6 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. (See page 10 for VDD = 2.3 V to 3.6 V) PARAMETER TEST CONDITIONS LIMITS MIN 3.6 Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS no load; VI = VDD or VSS -- -- -- -0.5 0.7VDD VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VDD VI = VSS 3 6 -10 -- -- -0.5 0.7VDD pin at VDD or VSS VI = VSS VCC = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA Vswin = VDD = 5.0 V; Iswout = -100 A Vswin = VDD = 4.5 V to 5.5 V; Iswout = -100 A VI = VDD or VSS VI = VSS -1 -- 4 -- 2.6 -10 -- TYP -- 570 250 1.7 -- -- -- -- -- -- 12 -- -- -- 2 11 3.5 -- -- 3 MAX 5.5 600 300 2.1 0.3VDD 6 -- -- +10 100 13 +0.3VDD VDD + 0.5 +50 3 24 -- 4.5 +100 5 UNIT
V A A V V V mA mA A A pF V V A pF V V A pF
Power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level LOW level output current LOW-level input current HIGH-level input current Input capacitance LOW-level input voltage HIGH-level input voltage Input leakage current Input capacitance Switch resistance Switch output voltage Leakage current Input/output capacitance
Input SCL; input/output SDA
Select inputs A0 to A2 / RESET
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
AC CHARACTERISTICS
SYMBOL tpd fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tR tF Cb tSP tVD:DATL tVD:DATH tVD:ACK RESET tWL(rst) trst tREC:STA Pulse width low reset Reset time (SDA clear) Recovery to Start 4 500 0 -- -- -- 4 500 0 -- -- -- ns ns ns PARAMETER Propagation delay from SDA to SDn or SCL to SCn SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Set-up time for STOP condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter Data valid (HL) Data valid (LH) Data valid Acknowledge STANDARD-MODE I2C-BUS MIN -- 0 4.7 4.0 4.7 4.0 4.7 4.0 02 250 -- -- -- -- -- -- -- MAX 0.31 100 -- -- -- -- -- -- 3.45 -- 1000 300 400 50 1 0.6 1 FAST-MODE I2C-BUS MIN -- 0 1.3 0.6 1.3 0.6 0.6 0.6 02 100 20 + 0.1Cb3 20 + 0.1Cb3 -- -- -- -- -- MAX 0.31 400 -- -- -- -- -- -- 0.9 -- 300 300 400 50 1 0.6 1 ns kHz s s s s s s s ns ns s s ns s s s UNIT
NOTES: 1. Pass gate propagation delay is calculated from the 20 typical RON and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 13. Definition of timing on the
I2C-bus
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
2004 Sep 30
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
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14
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
2004 Sep 30
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Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
REVISION HISTORY
Rev _2 Date 20040930 Description Product data sheet (9397 750 14123). Supersedes data of 2002 Feb 19 (9397 750 09459).
* Table 1, "Control register; Write--Channel Selection / Read--Channel Status": add `No channel selected;
power-up/reset default state' row to bottom of table. _1 20020219 Product data (9397 750 09459). ECN 853-2317 27757 of 19 February 2002.
Modifications:
2004 Sep 30
16
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data sheet
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data sheet
Qualification
III
Product data sheet
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Published in the U.S.A. Date of release: 09-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 14123
Philips Semiconductors
2004 Sep 30 17

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